// `include "stop_watch.v"
`default_nettype none

module stop_watch_tb;
reg        clk       ;//10MHz
reg        rst_n     ;
reg        clear     ;//清零按钮，上升沿有效
reg        start_stop;//开始/暂停按钮，上升沿有效
wire [3:0] hr_h      ;
wire [3:0] hr_l      ;
wire [3:0] min_h     ;
wire [3:0] min_l     ;
wire [3:0] sec_h     ;
wire [3:0] sec_l     ;


localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;

initial begin
    $dumpfile("sim/build/stop_watch_tb.vcd");
    $dumpvars(0, stop_watch_tb);
end

initial begin
    #1 rst_n<=1'bx;clk<=1'bx;clear<=1'bx;start_stop<=1'bx;         // 初始化
    #(CLK_PERIOD*3) rst_n<=1;
    #(CLK_PERIOD*3) rst_n<=0;clk<=0;clear<=1'b0;start_stop<=1'b0;  // 测试复位信号有效

    repeat(5) @(posedge clk);
    rst_n<=1;
    @(posedge clk);                                                // 启动
    start_stop<=1'b1;
    @(posedge clk);
    repeat(1000) @(posedge clk);                                   // 运行，覆盖了所有计数器
    #1;clear<=1'b1;                                                // 测试清零按键，上升沿有效
    @(posedge clk);
    #1;clear<=1'b0;                                                // clear无效，但此时状态为stop
    repeat(50) @(posedge clk);
    start_stop<=1'b0;
    @(posedge clk);
    #1;start_stop<=1'b1;
    @(posedge clk);                                                // 按键切换，状态切换为start
    repeat(500) @(posedge clk);
    #1;start_stop<=1'b0;
    repeat(50) @(posedge clk);
    #1;start_stop<=1'b1;                                           // 按键切换，状态切换为stop
    @(posedge clk);
    repeat(500) @(posedge clk);
    $finish(2);
end

stop_watch u_stop_watch(
    .clk        (clk        ),
    .rst_n      (rst_n      ),
    .clear      (clear      ),
    .start_stop (start_stop ),
    .hr_h       (hr_h       ),
    .hr_l       (hr_l       ),
    .min_h      (min_h      ),
    .min_l      (min_l      ),
    .sec_h      (sec_h      ),
    .sec_l      (sec_l      )
);


endmodule
`default_nettype wire